Introduction:
An integrated circuit (IC) is fundamentally a collection of electronic devices including transistors, diodes and resistors that have been fabricated and electrically interconnected onto a small, flat chip of semiconductor material. Silicon (Si) is the most widely used semiconductor material for these circuits primarily because of its exceptional combination of electrical properties and remarkably low cost. While silicon dominates the industry, less common semiconductor chips are manufactured using gallium arsenide (GaAs) and germanium (Ge). Because these circuits are fabricated into one solid piece of material, the term solid state electronics is commonly used to denote these devices. Semiconductor devices such as integrated circuits form the basis for virtually all modern electronics products which collectively constitute the world’s largest industry. In fact, this sector surpassed the automobile industry in gross sales as early as 1998.
The integrated circuit was invented in 1959 and has been the subject of continual development ever since. The most fascinating aspect of microelectronics technology is the extraordinary number of devices that can be packed onto a single small chip. Over the years, various terms have been developed to define the level of integration and density of packing, such as large scale integration (LSI) and very large scale integration (VLSI). Although there is not complete agreement over the exact dividing lines between these levels, they generally correspond to specific periods during which the technology was introduced. In 1975, Gordon Moore formulated what has come to be known as Moore’s law, which states that the number of transistors the building blocks of logic and memory devices on an integrated circuit doubles approximately every two years. The predictive ability of this law has remained remarkably accurate to the present time. Today’s gigascale technology is capable of fabricating millions of transistors per square millimeter of processable area on the chip surface.
Recent advances in semiconductor technology include system on chip and three dimensional integrated circuits. System on chip refers to the fabrication of an integrated circuit that contains all of the components required in a computer. Conventional computers typically include multiple integrated circuits and other components that are interconnected on a printed circuit board. The system on chip concept minimizes assembly costs and power requirements for the computer. A three dimensional integrated circuit is an IC consisting of components that have both vertical and horizontal features, enabling faster operation because the average conduction distance between components is reduced compared with a two dimensional layer containing the same number of components. Intel Corporation’s Tri‑Gate technology uses three‑dimensional transistors with vertical fins that project upward from the silicon chip surface enabling switching speeds to be increased and power requirements to be reduced.
Although semiconducting materials have been used in electronics for a long time, it was the invention of the transistor in 1947 that set the stage for what would become one of the greatest technological advancements in all of history. Microelectronics has played an increasing role in our lives ever since integrated circuit technology became the foundation for calculators, wrist watches, controls for home appliances and automobiles, information systems, telecommunications, robotics, space travel, weaponry and personal computers. The major advantages of today’s ICs are their very small size and low cost. As fabrication technology becomes more advanced, the size of devices made such as transistors, diodes, resistors and capacitors continues to decrease. Consequently, more components can be put onto a chip which is a small piece of semiconducting material on which the circuit is fabricated. In addition, mass production and automation have helped reduce the cost of each completed circuit. Typical chips produced today have sizes that are as small as 0.5 by 0.5 millimeters and in rare cases can be more than 50 by 50 millimeters. In the past, no more than 100 devices could be fabricated on a single chip. New technologies now allow densities in the range of 10 million devices per chip. This magnitude of integration has been termed very large scale integration. Some of the most advanced ICs may contain more than 100 million devices, termed ultralarge scale integration (ULSI). The Intel Itanium processors, for example, recently surpassed 2 billion transistors. More recent advances include wafer scale integration (WSI) in which an entire silicon wafer is used to build a single device. This approach has been of greatest interest in the design of massively parallel supercomputers including three dimensional integrated circuits which use multiple layers of active circuits that maintain connections both horizontally and vertically.
The Critical Role of Clean Rooms in IC Manufacturing:
Clean rooms are absolutely essential for the production of most integrated circuits a fact that can be fully appreciated by noting the scale of manufacturing to be performed. Integrated circuits are typically a few millimeters in length and the smallest features in a transistor on the circuit may be as small as a few tens of nanometers. This size range is smaller than particles that we do not normally consider harmful such as dust, smoke, perfume and bacteria. However if these contaminants are present on a silicon wafer during processing they can seriously compromise the performance of the entire device. Thus it is essential that all potentially harmful particles be eliminated from the IC manufacturing environment. Much of the processing sequence for integrated circuits must be carried out in a clean room, the ambiance of which is more like a hospital operating room than a production factory. Cleanliness is dictated by the microscopic feature sizes in an IC, the scale of which continues to decrease with each passing year. Common airborne particles that are potential contaminants in IC processing can cause defects in the integrated circuits reducing yields and increasing costs. A clean room provides protection from these contaminants. The air is purified to remove most of the particles from the processing environment, temperature and humidity are also controlled. The clean room is air conditioned to a temperature of 21 degrees Celsius and 45 percent relative humidity. The air is passed through a high efficiency particulate air (HEPA) filter to capture particle contaminants.
There are various levels of clean rooms which are defined by the class of the room. Several classification systems are used to specify cleanliness with two outlined here: the ISO and US systems. In both systems, a number is used to indicate the number of particles of size 0.5 micrometers or greater in a specified volume of air. In the ISO system, the volume of air is 1 cubic meter whereas 1 cubic foot is used in the US system. An ISO class 5 clean room is required to maintain a count of particles of size 0.5 micrometers or greater at less than 3,520 particles per cubic meter. That corresponds to a US class 100 clean room which must maintain a count of particles of size 0.5 micrometers or greater at less than 100 particles per cubic foot. Since 1 foot equals 0.3048 meters, 1 meter is equivalent to approximately 3.28 feet and 1 cubic meter equals 35.2 cubic feet. Thus 100 particles per cubic foot is equivalent to 3,520 particles per cubic meter. Most clean rooms for microelectronics manufacturing range from Class 0.035 to Class 0.35 in the ISO system. Modern VLSI processing requires ISO class 4 or US class 10 clean rooms, which means that the number of particles of size equal to or greater than 0.5 micrometers is less than 352 particles per cubic meter or 10 particles per cubic foot. In comparison, the contamination level in modern hospitals is on the order of 350,000 particles per cubic meter. Outside air in a typical urban atmosphere contains 35,000,000 particles per cubic meter or 1,000,000 particles per cubic foot of size equal to or greater than 0.5 micrometers.
To obtain controlled atmospheres that are free from particulate contamination, all ventilating air is passed through a HEPA filter. The largest source of contaminants in a clean room is the workers themselves. Skin particles, hair, perfume, makeup, clothing, bacteria and viruses are given off naturally by people and in sufficiently large numbers to quickly compromise a Class 3.5 clean room. Humans are the biggest source of contaminants in IC processing; emanating from humans are bacteria, tobacco smoke, viruses, hair and other particles. For these reasons, most clean rooms require special coverings such as white laboratory coats, gloves and hairnets as well as the avoidance of perfumes and makeup. The most stringent clean rooms require full body coverings called bunny suits where workers are completely encased for extreme cleanliness requirements. There are other stringent precautions as well. For example, the use of a pencil or ballpoint pen can produce objectionable graphite particles, and special clean room paper is required to prevent the accumulation of paper particles in the air. Processing equipment is a second major source of contaminants, machinery produces wear particles, oil, dirt and similar contaminants. IC processing is usually accomplished in laminar flow hooded work areas which can be purified to greater levels of cleanliness than the general environment of the clean room. Clean rooms are designed such that the cleanliness at critical processing locations is greater than in the clean room in general achieved by directing filtered ventilating air so that it displaces ambient air and directs dust particles away from the process. In addition to the very pure atmosphere provided by the clean room, the chemicals and water used in IC processing must be very clean and free of particles. Modern practice requires that chemicals and water be filtered before using them.
Understanding Semiconductor Materials and Silicon:
As the name suggests, semiconductor materials have electrical properties that lie between those of conductors and insulators, exhibiting resistivities between 10⁻³ and 10⁸ ohm centimeters. Semiconductors have become the foundation for electronic devices because their electrical properties can be altered when controlled amounts of selected impurity atoms are added to their crystal structures. These impurity atoms, also known as dopants, have either one more valence electron (n type or negative, dopant) or one less valence electron (p type or positive, dopant) than the atoms in the semiconductor lattice. For silicon which is a Group IV element in the Periodic Table, typical n type and p type dopants include, respectively, phosphorus (Group V) and boron (Group III). The electrical operation of semiconductor devices can be controlled through the creation of regions with different doping types and concentrations.
Although the earliest electronic devices were fabricated on germanium, silicon has become the industry standard. The abundance of alternative forms of silicon in the Earth is second only to that of oxygen making it attractive economically. Silicon constitutes more than 95 percent of all semiconductor devices produced in the world. Silicon’s main advantage over germanium is its large energy gap of 1.1 electron volts compared with that of germanium at 0.66 electron volts. This energy gap allows silicon based devices to operate at temperatures of about 150 degrees Celsius higher than devices fabricated on germanium which operate at about 100 degrees Celsius. Another important processing advantage of silicon is that its oxide (silicon dioxide, SiO₂) is an excellent electrical insulator and can be used for both isolation and passivation purposes. By contrast, germanium oxide is water soluble and unsuitable for electronic devices. Furthermore the oxidized form of silicon allows the production of metal oxide semiconductor (MOS) devices which are the basis for MOS transistors. These materials make up memory devices, processors and the like and are by far the largest volume of semiconductor material produced worldwide.
The crystallographic structure of silicon is a diamond type face‑centered cubic structure. Miller indices are a useful notation for identifying planes and directions within a unit cell. A crystallographic plane is defined by the reciprocal of its intercepts with the three axes. Since anisotropic etchants preferentially remove material in certain crystallographic planes, the orientation of the silicon crystal in a wafer is an important consideration. In spite of its advantages, silicon has a larger energy gap (1.1 eV) than germanium and therefore has a higher maximum operating temperature about 200 degrees Celsius. This limitation has encouraged the development of compound semiconductors specifically gallium arsenide. Its major advantage over silicon is its ability to emit light, thus allowing the fabrication of devices such as lasers and light emitting diodes (LEDs). Devices fabricated on gallium arsenide also have much higher operating speeds than those fabricated on silicon. Some of gallium arsenide’s disadvantages are its considerably higher cost, greater processing complications and most critically the difficulty of growing high quality oxide layers.
Crystal Growing and Wafer Preparation:
Silicon occurs naturally in the forms of silicon dioxide and various silicates. It undergo a series of purification steps to become the high quality, defect free, single crystal material required for semiconductor device fabrication. The preparation of the silicon substrate can be divided into three steps: production of electronic grade silicon, crystal growing and shaping of silicon into wafers.
The process begins by heating silica and carbon together in an electric furnace which results in a 95 to 98 percent pure polycrystalline silicon known as metallurgical grade silicon (MGS). The major impurities in MGS include aluminum, calcium, carbon, iron and titanium. This material is converted to an alternative form commonly trichlorosilane by grinding the brittle MGS and reacting the silicon powders with anhydrous hydrogen chloride in a fluidized‑bed reactor at temperatures around 300 degrees Celsius. Trichlorosilane, although a gas in the reaction equation is a liquid at room temperature. Its low boiling point of 32 degrees Celsius permits it to be separated from the leftover impurities of MGS by fractional distillation. The final step involves the reduction of the purified trichlorosilane by means of hydrogen gas at temperatures up to 1000 degrees Celsius. The product of this reaction is electronic grade silicon (EGS) which is nearly 100 percent pure silicon.
Single crystal silicon usually is obtained through the Czochralski (CZ) process. The setup includes a furnace a mechanical apparatus for pulling the boule, a vacuum system and supporting controls. The furnace consists of a crucible and heating system contained in a vacuum chamber. Chunks of electronic grade silicon are placed in the crucible and heated to a temperature slightly above the melting point of silicon: 1410 degrees Celsius. Heating is by induction or resistance, the latter being used for large melt sizes. The molten silicon is doped before pulling begins to make the crystal either p type or n type. To initiate crystal growing, a seed crystal of silicon is dipped into the molten pool and then withdrawn upward under carefully controlled conditions. At first, the pulling rate is relatively rapid which causes a single crystal of silicon to solidify against the seed forming a thin neck. The velocity is then reduced causing the neck to grow into the desired larger diameter of the boule while maintaining its single crystal structure. In addition to pulling rate, rotation of the crucible and other process parameters are used to control boule size. Single crystal ingots of diameter up to 450 millimeters and up to 3 meters long can be produced.
It is important to avoid contamination of the silicon during crystal growing because contaminants even in small amounts can dramatically alter the electrical properties of silicon. To minimize unwanted reactions and the introduction of contaminants at elevated temperatures, the procedure is carried out either in an inert gas (argon or helium) or a vacuum. Choice of crucible material is also important, fused silica (SiO₂) although not perfect represents the best available material and is used almost exclusively. Gradual dissolution of the crucible introduces oxygen as an unwanted impurity in the silicon boule. Unfortunately, the level of oxygen in the melt increases during the process leading to a variation in concentration of the impurity throughout the length and diameter of the ingot.
A series of processing steps are used to reduce the boule into thin, disc shaped wafers. The steps can be grouped as follows: ingot preparation, wafer slicing and wafer preparation. In ingot preparation, the seed and tang ends of the ingot are first cut off as well as portions that do not meet strict resistivity and crystallographic requirements. Next cylindrical grinding shapes the ingot into a more perfect cylinder. One or more flats are then ground along the length of the ingot, after wafers are cut, these flats serve several functions: identification, orientation of the ICs relative to crystal structure and mechanical location during processing. The ingot is now sliced into wafers using an abrasive cutoff process with a very thin saw blade with diamond grit bonded to the internal diameter. Use of the inner diameter for slicing rather than the outer diameter provides better control over flatness, thickness, parallelism and surface characteristics. Wafers are cut to a thickness of around 0.4 to 0.7 millimeters, depending on diameter. For every wafer cut, a certain amount of silicon is wasted because of the kerf width of the saw blade, to minimize kerf loss, blades are made as thin as possible around 0.33 millimeters. Next, the rims of the wafers are rounded using contour grinding to reduce chipping and minimize accumulation of photoresist solutions. The wafers are then chemically etched to remove surface damage from slicing followed by a flat polishing operation using a slurry of very fine silica particles in an aqueous solution of sodium hydroxide. The sodium hydroxide oxidizes the Si wafer surface, and the abrasive particles remove the oxidized surface layers about 0.025 millimeters is removed from each side during polishing. Finally, the wafer is chemically cleaned to remove residues and organic films. Wafers are identified by a laser scribe mark produced by the manufacturer, which may take place on the front or back side, with an exclusion edge area of 3 to 10 millimeters reserved for scribe information such as lot numbers orientation and a unique wafer identification code. Wafers are typically processed in lots of 25 or 50 with 150 to 200 millimeter diameters or lots of 12 to 25 with 300 millimeter diameters. At this point, the single crystal silicon wafer is ready for the fabrication of the integrated circuit.
Overview of IC Processing and Layering:
Structurally an integrated circuit consists of hundreds, thousands, millions or billions of microscopic electronic devices that have been fabricated and electrically interconnected within the surface of a silicon chip. A chip, also called a die is a square or rectangular flat plate that is about 0.5 millimeters thick and typically 5 to 25 millimeters on a side. Each electronic device on the chip surface consists of separate layers and regions with different electrical properties combined to perform the particular electronic function of the device. A typical cross section of a MOSFET device shows feature sizes as small as 32 nanometers currently, with 22 nanometers expected within a few years. The devices are electrically connected to one another by very fine lines of conducting material so that the interconnected devices function in the specified way. Conducting lines and pads are also provided to electrically connect the IC to leads, which in turn permit the IC to be connected to external circuits. MOSFET is the most important device technology for ultralarge scale integration.
The sequence to fabricate a silicon based IC chip consists of several types of processes, most of them repeated many times. A total of 200 or more processing steps may be required to produce a modern IC. Basically, the objective is to add, alter or remove a layer of material in selected regions of the wafer surface. The layering steps in IC fabrication are sometimes referred to as the planar process because the processing relies on the geometric form of the silicon wafer being a plane. The processes by which layers are added include thin film deposition techniques such as physical vapor deposition and chemical vapor deposition and existing layers are altered by diffusion and ion implantation. Additional layer forming techniques such as thermal oxidation are also employed. Layers are removed in selected regions by etching, using chemical etchants usually acid solutions and other advanced technologies such as plasma etching. The addition, alteration and removal of layers must be done selectively meaning only in certain extremely small regions of the wafer surface to create the device details. To distinguish which regions will be affected in each processing step a procedure involving lithography is used where masks are formed on the surface to protect certain areas and allow other areas to be exposed to the particular process. By repeating the steps many times, the starting silicon wafer is gradually transformed into many integrated circuits.
Processing of the wafer is organized so that many individual chip surfaces are formed on a single wafer. Because the wafer is round with diameters ranging from 150 to 450 millimeters whereas the final chip may only be 12 millimeters square, it is possible to produce hundreds of chips on a single wafer. At the conclusion of planar processing, each IC on the wafer is visually and functionally tested, the wafer is cut into individual chips and each chip that passes quality tests is packaged.
Film Deposition Techniques:
Films of many different types are used extensively in microelectronic device processing, particularly insulating and conducting films. Commonly deposited films include polysilicon, silicon nitride, silicon dioxide, tungsten, titanium and aluminum. In some instances, the wafers merely serve as a mechanical support on which custom epitaxial layers are grown. Epitaxy is defined as the growth of a vapor deposit that occurs when the crystal orientation of the deposit is related directly to the crystal orientation in the underlying crystalline substrate. The advantages of processing on these deposited films include fewer impurities, improved device performance and the tailoring of material properties which cannot be done on the wafers themselves. Major functions of deposited films are masking and protecting the semiconductor surface, in masking applications, the film must inhibit the passage of dopants and display an ability to be etched into patterns of high resolution. Films used for masking and protecting include silicon dioxide, phosphosilicate glass (PSG) and silicon nitride often used in combination. Conductive films used primarily for device interconnection must have low resistivity, be capable of carrying large currents and be suitable for connection to terminal packaging leads with wire bonds. Generally, aluminum and copper are used for this purpose. Increasing circuit complexity has required up to six levels of conductive layers, all separated by insulating films.
One of the simplest deposition methods is evaporation, used primarily for depositing metal films, where the metal is heated in a vacuum to its point of vaporization and forms a thin layer on the substrate surface, with heat generated by a heating filament or electron beam. Sputtering involves bombarding a target with high energy argon ions in a vacuum as ions impinge on the target, atoms are knocked off and deposited on wafers. Although some argon may be trapped within the film, sputtering results in highly uniform coverage. Advances include radio‑frequency power sources (RF sputtering) and introducing magnetic fields (magnetron sputtering). In chemical vapor deposition (CVD), film is deposited by reaction and decomposition of gaseous compounds, silicon dioxide is routinely deposited by oxidation of silane or a chlorosilane. A continuous CVD reactor operates at atmospheric pressure while low pressure CVD (LPCVD) operates at lower pressures, coating hundreds of wafers at a time with higher production rates and superior film uniformity. LPCVD is commonly used for depositing polysilicon, silicon nitride and silicon dioxide. Plasma enhanced CVD (PECVD) processes wafers in an RF plasma containing source gases, maintaining a low wafer temperature during deposition. Silicon epitaxy layers can be grown by vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), or molecular beam epitaxy (MBE). MBE results in very high purity and excellent control over doping profiles, important especially in gallium arsenide technology but has relatively low growth rates.
Oxidation and Its Applications:
The term oxidation refers to the growth of an oxide layer as a result of the reaction of oxygen with the substrate material. Oxide films can also be formed by deposition techniques but thermally grown oxides display a higher level of purity because they are grown directly from the high quality substrate. Silicon dioxide is the most widely used oxide in IC technology today and its excellent characteristics are a major reason for the widespread use of silicon. Aside from its effectiveness in dopant masking and device isolation, silicon dioxide’s most critical role is that of the gate oxide material. Silicon surfaces have an extremely high affinity for oxygen, and a freshly sawed slice of silicon will grow a native oxide of 30 to 40 angstroms thickness quickly.
Dry oxidation is accomplished by elevating the substrate temperature typically to about 750 to 1100 degrees Celsius in an oxygen rich environment. As a layer of oxide forms, the oxidizing agents must pass through the oxide and reach the silicon surface, where the actual reaction takes place. An oxide layer does not continue to grow on top of itself but rather grows from the silicon surface outward, consuming some of the silicon substrate. The ratio of oxide thickness to the amount of silicon consumed is 1 to 0.44; to obtain an oxide layer 1000 angstroms thick, approximately 440 angstroms of silicon will be consumed. One important effect of consumption is the rearrangement of dopants near the interface, because different impurities have different segregation coefficients or mobilities in silicon dioxide, some dopants become depleted while others pile up requiring adjustment of processing parameters.
Wet oxidation utilizes a water vapor atmosphere and results in a considerably higher growth rate than dry oxidation but suffers from lower oxide density and lower dielectric strength. The common practice combines both methods by growing an oxide in a three‑part layer, dry wet dry combining wet oxidation’s higher growth rate with dry oxidation’s high quality. The foregoing methods are useful primarily for coating the entire silicon surface but it may be necessary to oxidize only certain portions. Selective oxidation uses silicon nitride which inhibits the passage of oxygen and water vapor by covering certain areas with nitride, the silicon under these areas remains unaffected while uncovered areas are oxidized. When a silicon dioxide film must be applied to surfaces other than silicon, direct thermal oxidation is not appropriate and an alternative such as CVD must be used.
Lithography:
Lithography is the process by which geometric patterns that define devices are transferred to the substrate surface. There are many forms of lithography but the most common is photolithography. Electron beam and X ray lithography are of great interest because of their ability to transfer patterns of higher resolution, necessary for increased miniaturization. Photolithography uses a reticle, a glass or quartz plate with a pattern of the chip deposited onto it with a chromium film. The reticle image can be the same size as the desired structure but is often an enlarged image usually 5 to 20 times larger with 10 times magnification being most common. Enlarged images are focused onto a wafer through a lens system, an operation called reduction lithography. In current practice, the lithographic process is applied to each microelectronic circuit as many as 25 times each time using a different reticle to define different areas of the working devices. Typically designed at several thousand times their final size, reticle patterns undergo reductions before being applied to a defect free quartz plate. Computer aided design has had a major impact on reticle design and generation. Cleanliness is especially important and many manufacturers use robotics to minimize contamination.
Once film deposition is completed and reticle patterns are generated, the wafer is cleaned and coated with an organic polymer known as a photoresist (PR). A photoresist consists of three principal components: a polymer that changes structure when exposed to radiation, a sensitizer that controls reactions and a solvent to deliver the polymer in liquid form. Photoresist layers 0.5 to 2.5 micrometers thick are produced by applying the PR and spinning it at several thousand rpm for 30 or 60 seconds. The next step is prebaking the wafer on a hot plate around 100 degrees Celsius to remove solvent and harden the resist. The pattern is transferred through stepper or step and scan systems. With wafer steppers, the full image is exposed in one flash and the reticle pattern is refocused onto another adjacent section. With step and scan systems, the exposing light source is focused into a line and reticle and wafer are translated simultaneously in opposite directions. The wafer must be carefully aligned under the desired reticle in a crucial step called registration where the reticle must align with the previous layer. Upon exposure to ultraviolet radiation and development, a duplicate of the reticle pattern appears in the photoresist layer. The reticle can be a negative or positive image; positive reticles use UV radiation to break down the organic film so these films are removed preferentially by the developer. Positive masking is more common than negative masking because negative photoresist can swell and distort. Following exposure and development, postbaking drives off solvent and improves adhesion; a deep UV treatment at 150 to 200 degrees Celsius further strengthens the resist. The underlying film not covered by photoresist is then etched away or implanted. After lithography, the developed photoresist must be removed in a process called stripping. Wet stripping uses solutions like acetone or strong acids, dry stripping (ashing) exposes the photoresist to oxygen plasma and has become more popular because it avoids hazardous chemical disposal and offers easier control.
One major issue is line width, the smallest feature imprintable. Today, commercially feasible minimum line widths are 45 nanometers, with research directed at 32 nanometers or smaller. Pattern resolution has been limited by radiation wavelength, driving the need for shorter wavelengths like deep UV, extreme UV, electron beams and X‑rays. Extreme ultraviolet lithography (EUV) uses light at 13 nanometers to obtain features from 30 to 100 nanometers, focused through reflective molybdenum silicon mirrors. X ray lithography is superior due to shorter wavelength and very large depth of focus allowing aspect ratios higher than 100 compared to around 10 for photolithography but requires expensive synchrotron radiation and industry has preferred refining optical lithography. Electron beam and ion beam lithography involve high current density in narrow beams scanning a pattern one pixel at a time, offering accurate control, large depth of focus and low defect densities. Resolutions are limited to about 10 nanometers because of electron scatter, though 2 nanometers has been reported. The main drawbacks are vacuum requirements and much slower scan times. The SCALPEL process uses a mask of a 0.1 micrometer thick silicon nitride membrane patterned with a 50 nanometer thick tungsten coating, high energy electrons pass through both, but tungsten scatters widely while nitride scatters little and an aperture blocks scattered electrons to produce a high quality image. The limitation is small sized masks but the advantage is that energy does not need to be absorbed by the reticle.
Etching:
Etching removes entire films or particular sections playing an important role in fabrication. Key criteria include selectivity the ability to etch one material without etching another. In silicon technology, the process must etch silicon dioxide effectively with minimal removal of underlying silicon or resist. Polysilicon and metals must be etched into high resolution lines with vertical wall profiles and minimal removal of underlying insulating film or photoresist. Typical etch rates range from hundreds to thousands of angstroms per minute, and selectivities can range from 1:1 to 100:1. The two main categories are wet chemical etching and dry plasma etching.
Wet chemical etching uses an aqueous solution usually an acid to etch away a target material, selected because it attacks the specific material and not the protective mask. In its simplest form, masked wafers are immersed in an etchant for a specified time and immediately rinsed. Process variables such as immersion time, concentration and temperature are important. A properly etched layer will have an isotropic profile proceeding equally in all directions and resulting in an undercut below the protective mask, so mask patterns must be sized to compensate. In the ideal case, an etching solution reacts only with the target material, in practice, other materials may be attacked to a lesser degree. Etch selectivity is the ratio of etching rates between target material and another material. If process control is inadequate, under etching (target layer not completely removed) occurs if time is too short or solution too weak while over etching removes too much material, causing loss of pattern definition and possible damage to the layer beneath.
Dry plasma etching uses an ionized gas created by introducing an appropriate gas mixture into a vacuum chamber and using radio frequency electrical energy to create a plasma. The high energy plasma reacts with the target surface, vaporizing material. In plasma etching, the ionized gas generates chemically reactive atoms or molecules usually based on fluorine or chlorine gases, etch selectivity is generally more of a problem than wet etching. Alternatively, the ionized gas can physically bombard the target, causing atoms to be ejected, this is sputtering and when used for etching is called sputter etching. More commonly, sputtering is combined with plasma etching in reactive ion etching, producing both chemical and physical etching. The advantage of plasma processes is they are much more anisotropic. A fully anisotropic etch has zero undercut, anisotropy is defined as the ratio of depth to undercut. Wet etching yields anisotropy values around 1.0 (isotropic), sputter etching approaches infinity, plasma and reactive ion etching have high anisotropy but below sputter etching. As feature sizes shrink, anisotropy becomes increasingly important.
Diffusion and Ion Implantation:
The electrical operation of microelectronic devices depends on regions with different doping types and concentrations, altered through introduction of dopants into the substrate by diffusion and ion implantation. In diffusion, the movement of atoms results from thermal excitation. Dopants can be introduced as a deposited film or by placing the substrate in a vapor containing the dopant source, at elevated temperatures, usually 800 to 1200 degrees Celsius. Dopant movement is strictly a function of temperature, time, diffusion coefficient and substrate quality. Because of diffusion’s nature, dopant concentration is very high at the surface and drops off sharply, to obtain uniform concentration, the wafer is heated further in a drive in diffusion. Diffusion, whether desired or not always occurs at high temperatures. Although relatively inexpensive, diffusion is highly isotropic.
Ion implantation requires specialized equipment. Ions are accelerated through a high voltage field of as much as 1 million electron volts, and the desired dopant is selected by a mass separator. In a manner similar to cathode‑ray tubes, the beam is swept across the wafer by deflection plates, ensuring uniform coverage, and the operation is performed in vacuum. The high‑velocity impact damages the lattice structure, causing lower electron mobilities. This is repaired by annealing at relatively low temperatures, usually 400 to 800 degrees Celsius, for 15 to 30 minutes, which provides energy for the lattice to rearrange and mend. Another important function of annealing is driving in the implanted dopants; implantation alone imbeds them less than half a micron below the surface, while annealing enables diffusion to a more desirable depth of a few microns.
Metallization and Testing:
Conductive materials must be deposited to form certain components (e.g., gates), provide conduction paths between devices and connect the chip to external circuits. The process of fabricating these fine patterns is metallization, combining thin film deposition with optical lithography. Materials must have low resistivity, low contact resistance with silicon, good adherence to underlying material, ease of deposition compatible with lithography, chemical stability, physical stability during processing temperatures and good lifetime stability. Aluminum satisfies most requirements and is the most widely used material, usually alloyed with small amounts of silicon to reduce reactivity and copper to inhibit electromigration i.e. the physical movement of aluminum atoms by drifting electrons under high currents, which can sever or short lines. Solutions include sandwich layers of tungsten and titanium or using pure copper. Other materials include titanium, titanium nitride, copper, polysilicon, gold, refractory metals (W, Mo), silicides (WSi₂, MoSi₂, TaSi₂) and nitrides (TiN, TaN, ZrN). Aluminum is favored for device interconnections and top level connections.
Available metallization processes include PVD (vacuum evaporation and sputtering), CVD and electroplating. Evaporation is applied for aluminum but difficult for refractory metals, sputtering achieves better step coverage but lower deposition rates and higher equipment cost. CVD offers excellent step coverage and good rates for W, Mo, TiN, and silicides. Electroplating is occasionally used to increase film thickness. Modern ICs typically have one to six layers of metallization, each separated by a dielectric. Planarization of interlayer dielectrics is critical to reduce metal shorts and line width variation. A common method is a uniform oxide etch, but today’s standard is chemical‑mechanical polishing (CMP), combining an abrasive medium with a slurry to polish wafers to within 0.03 micrometers of perfectly flat with roughness on the order of 0.1 nanometers. Layers are connected by vias and contacts access devices.
Wafer processing is completed with a passivation layer of silicon nitride, acting as a barrier to sodium ions and providing scratch resistance. Each die is tested by a computer controlled probe platform with needle like probes accessing bonding pads. Probes are of two forms: test patterns or structures measuring processing parameters outside active dice and direct probe using 100% testing on bond pads. The platform scans the wafer with computer generated timing waveforms, defective chips are marked with ink. Up to one‑third of the cost can be incurred during testing. After testing, back grinding removes 25 to 75% of substrate thickness. Diamond sawing separates dice, with functional dice sent for packaging and inked dice discarded.
Wire Bonding and Packaging:
Working dice must be attached to a rugged foundation. One method fastens the die to packaging material with epoxy cement, another uses a eutectic bond made by heating metal alloy systems such as 96.4% gold and 3.6% silicon with a eutectic point at 370 degrees Celsius. Once attached, the chip is connected electrically to package leads by wire bonding very thin (25 micrometer diameter) gold wires from leads to bonding pads on the die, drawn at 75 to 100 micrometers per side. Bond wires are attached by thermocompression, ultrasonic, or thermosonic techniques.
Packages are available in many styles, reflecting operating requirements including chip size, number of leads, environment, heat dissipation and power. Military and industrial applications require high strength, toughness and temperature resistance. Packages are produced from polymers, metals or ceramics. Metal containers (e.g., Kovar, an iron cobalt nickel alloy) provide hermetic seals and good thermal conductivity but limit lead counts. Ceramic packages (aluminum oxide) are hermetic and have good thermal conductivity with higher lead counts but are more expensive. Plastic packages are inexpensive with high lead counts but have high thermal resistance and are not hermetic. Dual in line packages (DIP) are characterized by low cost and ease of handling, made of thermoplastics, epoxies or ceramics with 2 to 500 leads. Ceramic packages cost more for high reliability applications. Flat ceramic packages have all leads in the same plane for low‑profile applications. Surface mount packages are common; DIP connections use prongs inserted into holes while surface mounts solder onto fabricated pads. Faster chips require tighter connections. Pin grid arrays (PGAs) use pins through holes, but are susceptible to deformation. Ball grid arrays (BGAs) have solder plated metal balls on the underside, with spacing as small as 50 micrometers but standardized at 1.0, 1.27, or 1.5 mm. BGAs can have over 1000 connections but typically 200‑300 suffice. Reflow soldering centers the BGA by surface tension. After sealing, final testing involves heat, humidity, mechanical shock, corrosion and vibration.
Chip on board (COB) refers to direct placement of chips on an adhesive layer on a circuit board with wire bonding directly to pads, followed by epoxy encapsulation. Flip chip on board (FCOB) involves direct placement of a chip with solder bumps onto an array of pads saving space. System in package (SiP) incorporates more than one IC; vertical integration through stacked or embedded structures offers performance increases, reduced size, less noise, and better crosstalk isolation, though they require higher power density and extraction. SiP packages can be simple or complex, chips can be stacked with an interposing layer or interposerless structures using through silicon vias (TSVs) provide connections to all layers.
IC Packaging Design and Processing:
Packaging of integrated circuits is concerned with electrical connections to external circuits, materials to encase and protect from the environment like humidity, corrosion, temperature, vibration, shock, heat dissipation, performance, reliability, service life and cost. Manufacturing issues include chip separation, connecting to the package, encapsulating and testing. In design, the basic problem is connecting many internal circuits to input/output (I/O) terminals. As device count increases, required I/O terminals also increase. Package sealing materials: ceramic offers hermetic sealing and complex packages but has poor dimensional control.
Processing steps: Wafer testing uses multiprobe; defective chips are inked. Chip separation uses a diamond saw; the wafer is on adhesive tape. Die bonding attaches chips to packages: eutectic die bonding for ceramic (depositing gold on the chip, heating to >370°C, bonding) and epoxy die bonding for plastic (dispensing epoxy, positioning, curing). Wire bonding connects pads to leads using aluminum (0.05 mm) or gold (half that) wires, via ultrasonic, thermocompression or thermosonic bonding at up to 200 bonds/min. Package sealing: ceramic packages are formed from alumina sheets, laminated and sintered, plastic packages are post molded (transfer molding) or pre molded (base molded first). Final testing includes burn in at ~125°C for 24 hours, temperature cycling (−50°C to 125°C), vibration, and hermetic tests.
Yield and Reliability:
Yield is the ratio of functional chips to total chips produced. Overall yield is the product of wafer yield, bonding yield, packaging yield and test yield, ranging from a few percent for new processes to over 90% for mature lines. Most loss occurs during wafer processing due to point defects (oxide pinholes, metal particles, film contamination) and area defects (uneven deposition or nonuniform etch).
Reliability is measured by failure rate in FIT (one failure per 1 billion device hours). Complete systems have millions of devices, so overall failure rates are higher. Failure mechanisms include diffusion regions (nonuniform current, junction breakdown), oxide layers (dielectric breakdown, surface charge), lithography (uneven features, misalignment), metal layers (poor contact, electromigration), and improper mounting, wire bonds, or loss of hermetic seal. Accelerated life testing with cyclic variations in temperature, humidity, voltage, and current stresses components to predict failure modes and life under normal conditions.
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